Home  Product Directory  Electrical & Electronics  Telecommunication & Broadcasting  WiFi Products

Espressif Esp32 Agent Esp Agent Service Esp32 Technical Reference Manual

Negotiable 1 Piece (MOQ)

Min. Order:

1 Piece

Port:

Shenzhen, China

Production Capacity:

999999

Payment Terms:

T/T

Contact Now

Shenzhen Ferry Technology Co., Ltd

Guangdong, China

Last Login Date:

Aug 08, 2024

Business Type:

Manufacturer/Factory

Main Products:

Espressif Wi-Fi Bluetooth, Espressif Esp32-H2, Espressif Esp32-S3, Espressif Esp32-S2, Espressif Esp32-C6, Espressif Esp32-C2, Espressif Esp8266

Find Similar Products

Product Description

Company Info

Basic Info.

Type

WiFi Module

Work Mode

AP+STA

WiFi Antenna Type

Built-in

Transmission Rate

151-200Mbps

Voltage

3.3V

Antenna Gain

23dBi

Color

Black

Certification

RoHS, FCC, CE

Transport Package

Box

Product Description

If you need to buy more information about Espressif chip modules, solutions and other information, please feel free to send relevant information to our email,we will serve you wholeheartedly.

Espressif ESP32 agent esp agent service ESP32 Technical Reference Manual

ESP32
Technical Reference Manual

1System and Memory

1.1Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use the same addresses to access the same memory. Multiple peripherals in the system can access embedded memory via DMA.
The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and "application"), however, for most pur- poses the two CPUs are interchangeable.

1.2Features
•Address Space

-Symmetric address mapping
-4 GB (32-bit) address space for both data bus and instruction bus
-1296 KB embedded memory address space
-19704 KB external memory address space
-512 KB peripheral address space
-Some embedded and external memory regions can be accessed by either data bus or instruction bus
-328 KB DMA address space
•Embedded Memory

-448 KB Internal ROM
-520 KB Internal SRAM
-8 KB RTC FAST Memory
-8 KB RTC SLOW Memory
•External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the embedded memory can be used as transparent cache for this external memory.
-Supports up to 16 MB off-Chip SPI Flash.
-Supports up to 8 MB off-Chip SPI SRAM.
•Peripherals

-41 peripherals
•DMA

-13 modules are capable of DMA operation
The block diagram in Figure 1-1 illustrates the system structure, and the block diagram in Figure 1-2 illustrates the address map structure.

1.3Functional Description
1.3.1Address Mapping
Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are symmetric between the two CPUs.
Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~ 0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are shared by the data and instruction bus.
The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.
Each CPU can directly access embedded memory through both the data bus and the instruction bus, external memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1-1 illustrates address ranges that can be accessed by each CPU's data bus and instruction bus.
Some embedded memories and some external memories can be accessed via the data bus or the instruction bus. In these cases, the same memory is available to either of the CPUs at two address ranges.
Table 11. Address Mapping

Bus Type	Boundary Address		Size	Target
	Low Address	High Address
	0x0000_0000	0x3F3F_FFFF		Reserved
Data	0x3F40_0000	0x3F7F_FFFF	4 MB	External Memory
Data	0x3F80_0000	0x3FBF_FFFF	4 MB	External Memory
	0x3FC0_0000	0x3FEF_FFFF	3 MB	Reserved
Data	0x3FF0_0000	0x3FF7_FFFF	512 KB	Peripheral
Data	0x3FF8_0000	0x3FFF_FFFF	512 KB	Embedded Memory
Instruction	0x4000_0000	0x400C_1FFF	776 KB	Embedded Memory
Instruction	0x400C_2000	0x40BF_FFFF	11512 KB	External Memory
	0x40C0_0000	0x4FFF_FFFF	244 MB	Reserved
Data / Instruction	0x5000_0000	0x5000_1FFF	8 KB	Embedded Memory
	0x5000_2000	0xFFFF_FFFF		Reserved

1.3.2Embedded Memory
The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST memory (8 KB) and RTC SLOW memory (8 KB).
The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.
Table 1-2 lists all embedded memories and their address ranges on the data and instruction buses.
Table 12. Embedded Memory Address Mapping

Bus Type	Boundary Address		Size	Target	Comment
	Low Address	High Address
Data	0x3FF8_0000	0x3FF8_1FFF	8 KB	RTC FAST Memory	PRO_CPU Only
	0x3FF8_2000	0x3FF8_FFFF	56 KB	Reserved	-
Data	0x3FF9_0000	0x3FF9_FFFF	64 KB	Internal ROM 1	-
	0x3FFA_0000	0x3FFA_DFFF	56 KB	Reserved	-
Data	0x3FFA_E000	0x3FFD_FFFF	200 KB	Internal SRAM 2	DMA
Data	0x3FFE_0000	0x3FFF_FFFF	128 KB	Internal SRAM 1	DMA
Bus Type	Boundary Address		Size	Target	Comment
	Low Address	High Address
Instruction	0x4000_0000	0x4000_7FFF	32 KB	Internal ROM 0	Remap
Instruction	0x4000_8000	0x4005_FFFF	352 KB	Internal ROM 0	-
	0x4006_0000	0x4006_FFFF	64 KB	Reserved	-
Instruction	0x4007_0000	0x4007_FFFF	64 KB	Internal SRAM 0	Cache
Instruction	0x4008_0000	0x4009_FFFF	128 KB	Internal SRAM 0	-
Instruction	0x400A_0000	0x400A_FFFF	64 KB	Internal SRAM 1	-
Instruction	0x400B_0000	0x400B_7FFF	32 KB	Internal SRAM 1	Remap
Instruction	0x400B_8000	0x400B_FFFF	32 KB	Internal SRAM 1	-
Instruction	0x400C_0000	0x400C_1FFF	8 KB	RTC FAST Memory	PRO_CPU Only
Bus Type	Boundary Address		Size	Target	Comment
	Low Address	High Address
Data Instruc- tion	0x5000_0000	0x5000_1FFF	8 KB	RTC SLOW Memory	-

1.3.2.1Internal ROM 0
The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range 0x4000_0000
~ 0x4005_FFFF, which is on the instruction bus.
The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF. While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU, respectively.

1.3.2.2Internal ROM 1
The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.

1.3.2.3Internal SRAM 0
The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses

0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.

1.3.2.4Internal SRAM 1
The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses 0x3FFE_0000
~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the instruction bus.
The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word 0x3FFE_0004 and 0x400B_FFF8 access the same word 0x3FFE_0008 and 0x400B_FFF4 access the same word
...
0x3FFF_FFF4 and 0x400A_0008 access the same word 0x3FFF_FFF8 and 0x400A_0004 access the same word 0x3FFF_FFFC and 0x400A_0000 access the same word
The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
...
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.
Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more informa- tion.

1.3.2.5Internal SRAM 2
The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.

1.3.2.6DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2. This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.
In the ESP32, 13 peripherals are equipped with DMA. Table 1-3 lists these peripherals.

Table 13. Module with DMA

UART0	UART1		UART2
SPI1	SPI2		SPI3
I2S0		I2S1
SDIO Slave		SDMMC
EMAC
BT		WIFI

1.3.2.7RTC FAST Memory
RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of 0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the in- struction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the APP_CPU.
The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses 0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not provide access to RTC FAST Memory or any other memory location.

1.3.2.8RTC SLOW Memory
RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of 0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.

1.3.3External Memory
The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 1-4 provides a list of external memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When a CPU accesses external memory through the Cache and MMU, the cache will map the CPU's address to an external physical memory address (in the external memory's address space), according to the MMU settings. Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.
Table 14. External Memory Address Mapping

Bus Type	Boundary Address		Size	Target	Comment
	Low Address	High Address
Data	0x3F40_0000	0x3F7F_FFFF	4 MB	External Flash	Read
Data	0x3F80_0000	0x3FBF_FFFF	4 MB	External SRAM	Read and Write
Bus Type	Boundary Address		Size	Target	Comment
	Low Address	High Address
Instruction	0x400C_2000	0x40BF_FFFF	11512 KB	External Flash	Read

1.3.4Cache
As shown in Figure 1-3, each of the two CPUs in ESP32 has 32 KB of cache for accessing external storage. PRO CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG to enable the same function.

ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or APP CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select POOL0 or POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the Cache function, POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory, while they can also be used by the instruction bus. This is depicted in table 1-5 below.

Table 15. Cache memory mode

CACHE_MUX_MODE	POOL0	POOL1
0	PRO CPU	APP CPU
1	PRO CPU/APP CPU	-
2	-	PRO CPU/APP CPU
3	APP CPU	PRO CPU

As described in table 1-5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used as the cache memory, and cannot be used by the instruction bus as well.
ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1. Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be "PRO" or "APP", indicating that the cache flush operation has been completed.

For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and External Memory.

1.3.5Peripherals
The ESP32 has 41 peripherals. Table 1-6 specifically describes the peripherals and their respective address ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single exception; this being the PID Controller.
Table 16. Peripheral Address Mapping

Bus Type	Boundary Address		Size	Target	Comment
Bus Type	Low Address	High Address	Size	Target	Comment
Data	0x3FF0_0000	0x3FF0_0FFF	4 KB	DPort Register
Data	0x3FF0_1000	0x3FF0_1FFF	4 KB	AES Accelerator
Data	0x3FF0_2000	0x3FF0_2FFF	4 KB	RSA Accelerator
Data	0x3FF0_3000	0x3FF0_3FFF	4 KB	SHA Accelerator
Data	0x3FF0_4000	0x3FF0_4FFF	4 KB	Secure Boot
	0x3FF0_5000	0x3FF0_FFFF	44 KB	Reserved
Data	0x3FF1_0000	0x3FF1_3FFF	16 KB	Cache MMU Table
	0x3FF1_4000	0x3FF1_EFFF	44 KB	Reserved
Data	0x3FF1_F000	0x3FF1_FFFF	4 KB	PID Controller	Per-CPU peripheral
	0x3FF2_0000	0x3FF3_FFFF	128 KB	Reserved
Data	0x3FF4_0000	0x3FF4_0FFF	4 KB	UART0
	0x3FF4_1000	0x3FF4_1FFF	4 KB	Reserved
Data	0x3FF4_2000	0x3FF4_2FFF	4 KB	SPI1
Data	0x3FF4_3000	0x3FF4_3FFF	4 KB	SPI0
Data	0x3FF4_4000	0x3FF4_4FFF	4 KB	GPIO
	0x3FF4_5000	0x3FF4_7FFF	12 KB	Reserved
Data	0x3FF4_8000	0x3FF4_8FFF	4 KB	RTC
Data	0x3FF4_9000	0x3FF4_9FFF	4 KB	IO MUX
	0x3FF4_A000	0x3FF4_AFFF	4 KB	Reserved
Data	0x3FF4_B000	0x3FF4_BFFF	4 KB	SDIO Slave	One of three parts
Data	0x3FF4_C000	0x3FF4_CFFF	4 KB	UDMA1
	0x3FF4_D000	0x3FF4_EFFF	8 KB	Reserved
Data	0x3FF4_F000	0x3FF4_FFFF	4 KB	I2S0
Data	0x3FF5_0000	0x3FF5_0FFF	4 KB	UART1
	0x3FF5_1000	0x3FF5_2FFF	8 KB	Reserved
Data	0x3FF5_3000	0x3FF5_3FFF	4 KB	I2C0
Data	0x3FF5_4000	0x3FF5_4FFF	4 KB	UDMA0
Data	0x3FF5_5000	0x3FF5_5FFF	4 KB	SDIO Slave	One of three parts
Data	0x3FF5_6000	0x3FF5_6FFF	4 KB	RMT
Data	0x3FF5_7000	0x3FF5_7FFF	4 KB	PCNT
Data	0x3FF5_8000	0x3FF5_8FFF	4 KB	SDIO Slave	One of three parts
Data	0x3FF5_9000	0x3FF5_9FFF	4 KB	LED PWM
Data	0x3FF5_A000	0x3FF5_AFFF	4 KB	Efuse Controller
Data	0x3FF5_B000	0x3FF5_BFFF	4 KB	Flash Encryption

Bus Type	Boundary Address		Size	Target	Comment
Bus Type	Low Address	High Address	Size	Target	Comment
	0x3FF5_C000	0x3FF5_DFFF	8 KB	Reserved
Data	0x3FF5_E000	0x3FF5_EFFF	4 KB	PWM0
Data	0x3FF5_F000	0x3FF5_FFFF	4 KB	TIMG0
Data	0x3FF6_0000	0x3FF6_0FFF	4 KB	TIMG1
	0x3FF6_1000	0x3FF6_3FFF	12 KB	Reserved
Data	0x3FF6_4000	0x3FF6_4FFF	4 KB	SPI2
Data	0x3FF6_5000	0x3FF6_5FFF	4 KB	SPI3
Data	0x3FF6_6000	0x3FF6_6FFF	4 KB	SYSCON
Data	0x3FF6_7000	0x3FF6_7FFF	4 KB	I2C1
Data	0x3FF6_8000	0x3FF6_8FFF	4 KB	SDMMC
Data	0x3FF6_9000	0x3FF6_AFFF	8 KB	EMAC
	0x3FF6_B000	0x3FF6_BFFF	4 KB	Reserved
Data	0x3FF6_C000	0x3FF6_CFFF	4 KB	PWM1
Data	0x3FF6_D000	0x3FF6_DFFF	4 KB	I2S1
Data	0x3FF6_E000	0x3FF6_EFFF	4 KB	UART2
Data	0x3FF6_F000	0x3FF6_FFFF	4 KB	PWM2
Data	0x3FF7_0000	0x3FF7_0FFF	4 KB	PWM3
	0x3FF7_1000	0x3FF7_4FFF	16 KB	Reserved
Data	0x3FF7_5000	0x3FF7_5FFF	4 KB	RNG
	0x3FF7_6000	0x3FF7_FFFF	40 KB	Reserved

Notice:

•Peripherals accessed by the CPU via 0x3FF40000 ~ 0x3FF7FFFF address space (DPORT address) can also be accessed via 0x60000000 ~ 0x6003FFFF (AHB address). (0x3FF40000 + n) address and (0x60000000
+ n) address access the same content, where n = 0 ~ 0x3FFFF.
•The CPU can access peripherals via DPORT address more efficiently than via AHB address. However, DPORT address is characterized by speculative reads, which means it cannot guarantee that each read is valid. In addition, DPORT address will upset the order of r/w operations on the bus to improve performance, which may cause programs that have strict requirements on the r/w order to crash. On the other hand, using AHB address to read FIFO registers will cause unpredictable errors. To address above issues please strictly follow the instructions documented in ESP32 ECO and Workarounds for Bugs, specifically sections 3.3, 3.10, 3.16, and 3.17.

1.3.5.1Asymmetric PID Controller Peripheral
There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart. Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.

1.3.5.2NonContiguous Peripheral Memory Ranges
The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to ac- cess these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~

3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU's data bus. Similarly to other peripherals, access to this peripheral is identical for both CPUs.

1.3.5.3Memory Speed
The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access the SRAM at full speed, provided they access addresses in different memory banks.

2Interrupt Matrix (INTERRUPT)

2.1Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two CPUs' peripheral interrupts. This configuration is made to be highly flexible in order to meet many different needs.
2.2Features
•Accepts 71 peripheral interrupt sources as input.

•Generates 26 peripheral interrupt sources per CPU as output (52 total).

•CPU NMI Interrupt Mask.

Queries current interrupt status of peripheral interrupt sources.

2.3Functional Description
2.3.1Peripheral Interrupt Source
ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 2-1. 67 of 71 ESP32 peripheral interrupt sources can be allocated to either CPU.
The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and GPIO_INTERRUPT
_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each have 69 peripheral in- terrupt sources.

Table 21. PRO_CPU, APP_CPU Interrupt Configuration

PRO_CPU					APP_CPU
Peripheral Interrupt Configuration Register	Peripheral Interrupt Source								Peripheral Interrupt Configuration Register
	Status Register		No.	Name		No.	Status Register
	Bit	Name					Name	Bit
PRO_MAC_INTR_MAP_REG	0	PRO_INTR_STATUS_REG_0	0	MAC_INTR		0	APP_INTR_STATUS_REG_0	0	APP_MAC_INTR_MAP_REG
PRO_MAC_NMI_MAP_REG	1		1	MAC_NMI		1		1	APP_MAC_NMI_MAP_REG
PRO_BB_INT_MAP_REG	2		2	BB_INT		2		2	APP_BB_INT_MAP_REG
PRO_BT_MAC_INT_MAP_REG	3		3	BT_MAC_INT		3		3	APP_BT_MAC_INT_MAP_REG
PRO_BT_BB_INT_MAP_REG	4		4	BT_BB_INT		4		4	APP_BT_BB_INT_MAP_REG
PRO_BT_BB_NMI_MAP_REG	5		5	BT_BB_NMI		5		5	APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG	6		6	RWBT_IRQ		6		6	APP_RWBT_IRQ_MAP_REG
PRO_RWBLE_IRQ_MAP_REG	7		7	RWBLE_IRQ		7		7	APP_RWBLE_IRQ_MAP_REG
PRO_RWBT_NMI_MAP_REG	8		8	RWBT_NMI		8		8	APP_RWBT_NMI_MAP_REG
PRO_RWBLE_NMI_MAP_REG	9		9	RWBLE_NMI		9		9	APP_RWBLE_NMI_MAP_REG
PRO_SLC0_INTR_MAP_REG	10		10	SLC0_INTR		10		10	APP_SLC0_INTR_MAP_REG
PRO_SLC1_INTR_MAP_REG	11		11	SLC1_INTR		11		11	APP_SLC1_INTR_MAP_REG
PRO_UHCI0_INTR_MAP_REG	12		12	UHCI0_INTR		12		12	APP_UHCI0_INTR_MAP_REG
PRO_UHCI1_INTR_MAP_REG	13		13	UHCI1_INTR		13		13	APP_UHCI1_INTR_MAP_REG
PRO_TG_T0_LEVEL_INT_MAP_REG	14		14	TG_T0_LEVEL_INT		14		14	APP_TG_T0_LEVEL_INT_MAP_REG
PRO_TG_T1_LEVEL_INT_MAP_REG	15		15	TG_T1_LEVEL_INT		15		15	APP_TG_T1_LEVEL_INT_MAP_REG
PRO_TG_WDT_LEVEL_INT_MAP_REG	16		16	TG_WDT_LEVEL_INT		16		16	APP_TG_WDT_LEVEL_INT_MAP_REG
PRO_TG_LACT_LEVEL_INT_MAP_REG	17		17	TG_LACT_LEVEL_INT		17		17	APP_TG_LACT_LEVEL_INT_MAP_REG
PRO_TG1_T0_LEVEL_INT_MAP_REG	18		18	TG1_T0_LEVEL_INT		18		18	APP_TG1_T0_LEVEL_INT_MAP_REG
PRO_TG1_T1_LEVEL_INT_MAP_REG	19		19	TG1_T1_LEVEL_INT		19		19	APP_TG1_T1_LEVEL_INT_MAP_REG
PRO_TG1_WDT_LEVEL_INT_MAP_REG	20		20	TG1_WDT_LEVEL_INT		20		20	APP_TG1_WDT_LEVEL_INT_MAP_REG
PRO_TG1_LACT_LEVEL_INT_MAP_REG	21		21	TG1_LACT_LEVEL_INT		21		21	APP_TG1_LACT_LEVEL_INT_MAP_REG
PRO_GPIO_INTERRUPT_PRO_MAP_REG	22		22	GPIO_INTERRUPT_PRO	GPIO_INTERRUPT_APP	22		22	APP_GPIO_INTERRUPT_APP_MAP_REG
PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG	23		23	GPIO_INTERRUPT_PRO_NMI	GPIO_INTERRUPT_APP_NMI	23		23	APP_GPIO_INTERRUPT_APP_NMI_MAP_REG
PRO_CPU_INTR_FROM_CPU_0_MAP_REG	24		24	CPU_INTR_FROM_CPU_0		24		24	APP_CPU_INTR_FROM_CPU_0_MAP_REG
PRO_CPU_INTR_FROM_CPU_1_MAP_REG	25		25	CPU_INTR_FROM_CPU_1		25		25	APP_CPU_INTR_FROM_CPU_1_MAP_REG
PRO_CPU_INTR_FROM_CPU_2_MAP_REG	26		26	CPU_INTR_FROM_CPU_2		26		26	APP_CPU_INTR_FROM_CPU_2_MAP_REG
PRO_CPU_INTR_FROM_CPU_3_MAP_REG	27		27	CPU_INTR_FROM_CPU_3		27		27	APP_CPU_INTR_FROM_CPU_3_MAP_REG
PRO_SPI_INTR_0_MAP_REG	28		28	SPI_INTR_0		28		28	APP_SPI_INTR_0_MAP_REG
PRO_SPI_INTR_1_MAP_REG	29		29	SPI_INTR_1		29		29	APP_SPI_INTR_1_MAP_REG
PRO_SPI_INTR_2_MAP_REG	30		30	SPI_INTR_2		30		30	APP_SPI_INTR_2_MAP_REG
PRO_SPI_INTR_3_MAP_REG	31		31	SPI_INTR_3		31		31	APP_SPI_INTR_3_MAP_REG
PRO_I2S0_INT_MAP_REG	0	PRO_INTR_STATUS_REG_1	32	I2S0_INT		32	APP_INTR_STATUS_REG_1	0	APP_I2S0_INT_MAP_REG
PRO_I2S1_INT_MAP_REG	1		33	I2S1_INT		33		1	APP_I2S1_INT_MAP_REG
PRO_UART_INTR_MAP_REG	2		34	UART_INTR		34		2	APP_UART_INTR_MAP_REG
PRO_UART1_INTR_MAP_REG	3		35	UART1_INTR		35		3	APP_UART1_INTR_MAP_REG
PRO_UART2_INTR_MAP_REG	4		36	UART2_INTR		36		4	APP_UART2_INTR_MAP_REG
PRO_SDIO_HOST_INTERRUPT_MAP_REG	5		37	SDIO_HOST_INTERRUPT		37		5	APP_SDIO_HOST_INTERRUPT_MAP_REG
PRO_EMAC_INT_MAP_REG	6		38	EMAC_INT		38		6	APP_EMAC_INT_MAP_REG
PRO_PWM0_INTR_MAP_REG	7		39	PWM0_INTR		39		7	APP_PWM0_INTR_MAP_REG
PRO_PWM1_INTR_MAP_REG	8		40	PWM1_INTR		40		8	APP_PWM1_INTR_MAP_REG
PRO_PWM2_INTR_MAP_REG	9		41	PWM2_INTR		41		9	APP_PWM2_INTR_MAP_REG
PRO_PWM3_INTR_MAP_REG	10		42	PWM3_INTR		42		10	APP_PWM3_INTR_MAP_REG
PRO_LEDC_INT_MAP_REG	11		43	LEDC_INT		43		11	APP_LEDC_INT_MAP_REG
PRO_EFUSE_INT_MAP_REG	12		44	EFUSE_INT		44		12	APP_EFUSE_INT_MAP_REG
PRO_CAN_INT_MAP_REG	13		45	CAN_INT		45		13	APP_CAN_INT_MAP_REG
PRO_RTC_CORE_INTR_MAP_REG	14		46	RTC_CORE_INTR		46		14	APP_RTC_CORE_INTR_MAP_REG
PRO_RMT_INTR_MAP_REG	15		47	RMT_INTR		47		15	APP_RMT_INTR_MAP_REG
PRO_PCNT_INTR_MAP_REG	16		48	PCNT_INTR		48		16	APP_PCNT_INTR_MAP_REG
PRO_I2C_EXT0_INTR_MAP_REG	17		49	I2C_EXT0_INTR		49		17	APP_I2C_EXT0_INTR_MAP_REG
PRO_I2C_EXT1_INTR_MAP_REG	18		50	I2C_EXT1_INTR		50		18	APP_I2C_EXT1_INTR_MAP_REG
PRO_RSA_INTR_MAP_REG	19		51	RSA_INTR		51		19	APP_RSA_INTR_MAP_REG
PRO_SPI1_DMA_INT_MAP_REG	20		52	SPI1_DMA_INT		52		20	APP_SPI1_DMA_INT_MAP_REG

PRO_CPU					APP_CPU
Peripheral Interrupt Configuration Register	Peripheral Interrupt Source								Peripheral Interrupt Configuration Register
	Status Register		No.	Name		No.	Status Register
	Bit	Name					Name	Bit
PRO_SPI2_DMA_INT_MAP_REG	21	PRO_INTR_STATUS_REG_1	53	SPI2_DMA_INT		53	APP_INTR_STATUS_REG_1	21	APP_SPI2_DMA_INT_MAP_REG
PRO_SPI3_DMA_INT_MAP_REG	22		54	SPI3_DMA_INT		54		22	APP_SPI3_DMA_INT_MAP_REG
PRO_WDG_INT_MAP_REG	23		55	WDG_INT		55		23	APP_WDG_INT_MAP_REG
PRO_TIMER_INT1_MAP_REG	24		56	TIMER_INT1		56		24	APP_TIMER_INT1_MAP_REG
PRO_TIMER_INT2_MAP_REG	25		57	TIMER_INT2		57		25	APP_TIMER_INT2_MAP_REG
PRO_TG_T0_EDGE_INT_MAP_REG	26		58	TG_T0_EDGE_INT		58		26	APP_TG_T0_EDGE_INT_MAP_REG
PRO_TG_T1_EDGE_INT_MAP_REG	27		59	TG_T1_EDGE_INT		59		27	APP_TG_T1_EDGE_INT_MAP_REG
PRO_TG_WDT_EDGE_INT_MAP_REG	28		60	TG_WDT_EDGE_INT		60		28	APP_TG_WDT_EDGE_INT_MAP_REG
PRO_TG_LACT_EDGE_INT_MAP_REG	29		61	TG_LACT_EDGE_INT		61		29	APP_TG_LACT_EDGE_INT_MAP_REG
PRO_TG1_T0_EDGE_INT_MAP_REG	30		62	TG1_T0_EDGE_INT		62		30	APP_TG1_T0_EDGE_INT_MAP_REG
PRO_TG1_T1_EDGE_INT_MAP_REG	31		63	TG1_T1_EDGE_INT		63		31	APP_TG1_T1_EDGE_INT_MAP_REG
PRO_TG1_WDT_EDGE_INT_MAP_REG	0	PRO_INTR_STATUS_REG_2	64	TG1_WDT_EDGE_INT		64	APP_INTR_STATUS_REG_2	0	APP_TG1_WDT_EDGE_INT_MAP_REG
PRO_TG1_LACT_EDGE_INT_MAP_REG	1		65	TG1_LACT_EDGE_INT		65		1	APP_TG1_LACT_EDGE_INT_MAP_REG
PRO_MMU_IA_INT_MAP_REG	2		66	MMU_IA_INT		66		2	APP_MMU_IA_INT_MAP_REG
PRO_MPU_IA_INT_MAP_REG	3		67	MPU_IA_INT		67		3	APP_MPU_IA_INT_MAP_REG
PRO_CACHE_IA_INT_MAP_REG	4		68	CACHE_IA_INT		68		4	APP_CACHE_IA_INT_MAP_REG

2.3.2CPU Interrupt
Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All interrupts in a CPU are listed in Table 2-2.
Table 22. CPU Interrupts

No.	Category	Type	Priority Level
0	Peripheral	Level-Triggered	1
1	Peripheral	Level-Triggered	1
2	Peripheral	Level-Triggered	1
3	Peripheral	Level-Triggered	1
4	Peripheral	Level-Triggered	1
5	Peripheral	Level-Triggered	1
6	Internal	Timer.0	1
7	Internal	Software	1
8	Peripheral	Level-Triggered	1
9	Peripheral	Level-Triggered	1
10	Peripheral	Edge-Triggered	1
11	Internal	Profiling	3
12	Peripheral	Level-Triggered	1
13	Peripheral	Level-Triggered	1
14	Peripheral	NMI	NMI
15	Internal	Timer.1	3
16	Internal	Timer.2	5
17	Peripheral	Level-Triggered	1
18	Peripheral	Level-Triggered	1
19	Peripheral	Level-Triggered	2
20	Peripheral	Level-Triggered	2
21	Peripheral	Level-Triggered	2
22	Peripheral	Edge-Triggered	3
23	Peripheral	Level-Triggered	3
24	Peripheral	Level-Triggered	4
25	Peripheral	Level-Triggered	4
26	Peripheral	Level-Triggered	5
27	Peripheral	Level-Triggered	3
28	Peripheral	Edge-Triggered	4
29	Internal	Software	3
30	Peripheral	Edge-Triggered	4
31	Peripheral	Level-Triggered	5

2.3.3Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU
In this section:

•Source_X stands for any particular peripheral interrupt source.

•PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration register

of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the peripheral interrupt source Source_X. In Table 2-1 the registers listed under "PRO_CPU (APP_CPU) - Peripheral Interrupt Configuration Register" correspond to the peripheral interrupt sources listed in "Peripheral Interrupt Source
- Name".

•Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8
~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.
•Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15, 16, 29.
Using this terminology, the possible operations of the Interrupt Matrix controller can be described as follows:

•Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG or APP_X_MAP_REG to Num_P. Num_P can be any CPU peripheral interrupt num- ber. CPU interrupts can be shared between multiple peripherals (see below).
•Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG or APP_X _MAP_REG for peripheral interrupt source to any Num_I. The specific choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as Num_I is connected to either CPU.
•Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral interrupts will trigger CPU Interrupt_P.

2.3.4CPU NMI Interrupt Mask
The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU's ( or APP_CPU's ) NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the peripheral PID Controller, respectively.

2.3.5Query Current Interrupt Status of Peripheral Interrupt Source
The current interrupt status of a peripheral interrupt source can be read via the bit value in PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 2-1.

2.4Registers
The interrupt matrix registers are part of the DPORT registers and are described in Section 5.4 in Chapter 5 DPort Registers.

Address: Baoan Internet Industry Base, Zao Community, Xixiang Street, Bao ′an District, Shenzhen, Guangdong, China

Business Type: Manufacturer/Factory

Business Range: Consumer Electronics, Electrical & Electronics, Industrial Equipment & Components, Light Industry & Daily Use, Lights & Lighting, Manufacturing & Processing Machinery, Service

Management System Certification: ISO 9001, ISO 9000

Main Products: Espressif Wi-Fi Bluetooth, Espressif Esp32-H2, Espressif Esp32-S3, Espressif Esp32-S2, Espressif Esp32-C6, Espressif Esp32-C2, Espressif Esp8266

Company Introduction: Shenzhen Ferry Technology Co., Ltd. Has been focusing on the optimization and construction of wireless communication transmission mechanism and wireless audio and video transmission solution level to provide WiFi module company, unremitting in-depth development of WiFi wireless transmission, radar induction and other low-power IOT scene microwave radar manufacturers, We are committed to bringing rich and diverse data and information into every person, home, and organization in an easily accessible way, building a smart world that connects everything: Connecting everywhere and connecting our lives to each other; Let wireless transmission without boundaries, so that intelligence at your fingertips.

The comprehensive agent Espressif WiFi series products, Espressif ESP32-H2, Espressif ESP32-C6, Espressif ESP32-S3, Espressif ESP32-S2, Espressif ESP32-C2, Espressif ESP8266 and other products. Belong to the general agent qualification certificate is complete, welcome new and old customers to come to consult, we will serve you wholeheartedly.

Send your message to this supplier

Hot Searches

Service Switch

Manual Switch

Sourcing Service

Wifi Antenna

Oem Agent

Goods Agent

Ups Agent

Dhl Fedex Ups Tnt Agent

Source Agent

More

People who liked this also liked

Espressif Esp32 Agent Esp Agent Service Esp32 Technical Reference Manual

Product Description

Company Info

Basic Info.

Product Description

Hot Searches

Recommended Suppliers & Wholesalers