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Product Description

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Basic Info.

Model NO.

ESP32-S3 Series Datasheet

Type

WiFi Module

Work Mode

AP+STA

WiFi Antenna Type

Built-in

Transmission Rate

151-200Mbps

Voltage

3.3V

Antenna Gain

23dBi

Color

Black

Certification

RoHS, FCC, CE

Transport Package

Box

Product Description

If you need to buy more information about Espressif chip modules, solutions and other information, please feel free to send relevant information to our email,we will serve you wholeheartedly.

ESP32S3 Series
Datasheet

2.4GHz WiFi + Bluetooth® LE SoC
Supporting IEEE 802.11b/g/n (2.4 GHz WiFi) and Bluetooth 5 (LE)

Including:
ESP32-S3 ESP32-S3FN8 ESP32-S3R2 ESP32-S3R8 ESP32-S3R8V

Product Overview

ESP32-S3 is a low-power MCU-based SoC that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core MCU (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and peripherals. The block diagram of the SoC is shown below.

Solution Highlights
•A complete WiFi subsystem that complies with IEEE 802.11b/g/n protocol and supports Station, SoftAP, and SoftAP + Station modes
•A Bluetooth LE subsystem that supports

features of Bluetooth 5 and Bluetooth mesh
•Xtensa® 32bit LX7 dualcore processor with a five-stage pipeline that operates at up to 240 MHz

-A 128-bit data bus and dedicated SIMD instructions to provide high computing performance
-Efficient L1 cache to improve execution of external memory
-Single-precision floating-point unit (FPU) to accelerate computing
•Highlyintegrated RF module that provides industry-leading power and RF performance
•Stateoftheart power management designed for a wide range of applications with its multiple low-power modes. The ULP coprocessor can operate in ultra-low-power mode.
•Powerful storage capacities ensured by 512 KB SRAM and 384 KB ROM on the chip, and

SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI interfaces that allow connection to flash and external RAM
•Reliable security features ensured by
-Cryptographic hardware accelerators that support AES-128/256, Hash, RSA, HMAC, digital signature, and secure boot
-Random number generator
-Permission control on accessing internal and external memory
-External memory encryption and decryption
•Rich set of peripheral interfaces and GPIOs, ideal for various scenarios and complex applications

Features
WiFi

•IEEE 802.11 b/g/n-compliant
•Supports 20 MHz, 40 MHz bandwidth in 2.4 GHz band
•1T1R mode with data rate up to 150 Mbps
•Wi-Fi Multimedia (WMM)
•TX/RX A-MPDU, TX/RX A-MSDU
•Immediate Block ACK
•Fragmentation and defragmentation
•Automatic Beacon monitoring (hardware TSF)
•4 × virtual Wi-Fi interfaces
•Simultaneous support for Infrastructure BSS in Station, SoftAP, or Station + SoftAP modes Note that when ESP32-S3 scans in Station
mode, the SoftAP channel will change along with the Station channel
•Antenna diversity
•802.11mc FTM
•External PA is supported

Bluetooth

•Bluetooth LE: Bluetooth 5, Bluetooth mesh
•High power mode (20 dBm, share the same PA with Wi-Fi)
•2 Mbps PHY
•Long range mode
•Advertising extensions
•Multiple advertisement sets
•Channel selection algorithm #2
•Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna

CPU and Memory

•Xtensa® dual-core 32-bit LX7 microprocessor, up to 240 MHz
•CoreMark® score:
-1 core at 240 MHz: 613.86 CoreMark; 2.56 CoreMark/MHz
-2 cores at 240 MHz: 1181.60 CoreMark;
4.92 CoreMark/MHz
•128-bit data bus and SIMD commands

•384 KB ROM
•512 KB SRAM
•16 KB SRAM in RTC
•SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to multiple flash and external RAM
•Flash controller with cache is supported
•Flash in-Circuit Programming (ICP) is supported

Advanced Peripheral Interfaces

•45 × programmable GPIOs
•Digital interfaces:
-4 × SPI
-1 × LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411
-1 × DVP 8-bit ~16-bit camera interface
-3 × UART
- 2 × I2C
- 2 × I2S
-1 × RMT (TX/RX)
-1 × pulse counter
-LED PWM controller, up to 8 channels
-1 × full-speed USB OTG
-1 × USB Serial/JTAG controller
-2 × MCPWM
-1 × SDIO host controller with 2 slots
-DMA controller, with 5 transmit channels and 5 receive channels

- 1 × TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
•Analog interfaces:
-2 × 12-bit SAR ADCs, up to 20 channels
-1 × temperature sensor
-14 × touch sensing IOs
•Timers:
-4 × 54-bit general-purpose timers
-1 × 52-bit system timer
-3 × watchdog timers

Low Power Management

•Power Management Unit with five power modes
•Ultra-Low-Power (ULP) coprocessors:
-ULP-RISC-V coprocessor
-ULP-FSM coprocessor

Security

•Secure boot
•Flash encryption
•4096-bit OTP, up to 1652 bits for users
•Cryptographic hardware acceleration:
- AES-128/256 (FIPS PUB 197)
-Hash (FIPS PUB 180-4)
-RSA
-Random Number Generator (RNG)
-HMAC
-Digital signature

Applications (A Nonexhaustive List)
With low power consumption, ESP32-S3 is an ideal choice for IoT devices in the following areas:

•Smart Home
-Light control
-Smart button
-Smart plug
•Industrial Automation
-Industrial robot
-Mesh network
-Human machine interface (HMI)
•Health Care
-Health monitor
-Baby monitor
•Consumer Electronics
-Smart watch and bracelet
-Over-the-top (OTT) devices
-Wi-Fi and bluetooth speaker
-Logger toys and proximity sensing toys
•Smart Agriculture
-Smart greenhouse
-Smart irrigation
-Agriculture robot
•Retail and Catering
-POS machines
-Service robot
•Audio Device
-Internet music players
-Live streaming devices
-Internet radio players
•Generic Low-power IoT Sensor Hubs
•Generic Low-power IoT Data Loggers
•Cameras for Video Streaming
•USB Devices
•Speech Recognition
•Image Recognition
•Wi-Fi + Bluetooth Networking Card
•Touch Sensing
-Waterproof design
-Distance sensing applications
Linear slider, wheel slider designs

2.2Pin Description

Name	No.	Type	Power Domain	Function
LNA_IN	1	I/O	-	Low Noise Amplifier(RF LNA) input and output signal
VDD3P3	2	P_A	-	Analog power supply
VDD3P3	3	P_A	-	Analog power supply
CHIP_PU	4	I	VDD3P3_RTC	High: on, enables the chip. Low: off, the chip powers off. Note: Do not leave the CHIP_PU pin floating.
GPIO0	5	I/O/T	VDD3P3_RTC	RTC_GPIO0, GPIO0
GPIO1	6	I/O/T	VDD3P3_RTC	RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
GPIO2	7	I/O/T	VDD3P3_RTC	RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
GPIO3	8	I/O/T	VDD3P3_RTC	RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
GPIO4	9	I/O/T	VDD3P3_RTC	RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
GPIO5	10	I/O/T	VDD3P3_RTC	RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
GPIO6	11	I/O/T	VDD3P3_RTC	RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
GPIO7	12	I/O/T	VDD3P3_RTC	RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
GPIO8	13	I/O/T	VDD3P3_RTC	RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
GPIO9	14	I/O/T	VDD3P3_RTC	RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, SUBSPIHD, FSPIHD
GPIO10	15	I/O/T	VDD3P3_RTC	RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPIIO4, SUBSPICS0, FSPICS0
GPIO11	16	I/O/T	VDD3P3_RTC	RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPIIO5, SUBSPID, FSPID
GPIO12	17	I/O/T	VDD3P3_RTC	RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPIIO6, SUBSPICLK, FSPICLK
GPIO13	18	I/O/T	VDD3P3_RTC	RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIIO7, SUBSPIQ, FSPIQ
GPIO14	19	I/O/T	VDD3P3_RTC	RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIDQS, SUBSPIWP, FSPIWP
VDD3P3_RTC	20	P_A	-	Analog power supply
XTAL_32K_P	21	I/O/T	VDD3P3_RTC	RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
XTAL_32K_N	22	I/O/T	VDD3P3_RTC	RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
GPIO17	23	I/O/T	VDD3P3_RTC	RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
GPIO18	24	I/O/T	VDD3P3_RTC	RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3

Name	No.	Type	Power Domain	Function
GPIO19	25	I/O/T	VDD3P3_RTC	RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
GPIO20	26	I/O/T	VDD3P3_RTC	RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
GPIO21	27	I/O/T	VDD3P3_RTC	RTC_GPIO21, GPIO21
SPICS1	28	I/O/T	VDD_SPI	SPICS1, GPIO26
VDD_SPI	29	P_D	-	Output power supply: 1.8 V or VDD3P3_RTC
SPIHD	30	I/O/T	VDD_SPI	SPIHD, GPIO27
SPIWP	31	I/O/T	VDD_SPI	SPIWP, GPIO28
SPICS0	32	I/O/T	VDD_SPI	SPICS0, GPIO29
SPICLK	33	I/O/T	VDD_SPI	SPICLK, GPIO30
SPIQ	34	I/O/T	VDD_SPI	SPIQ, GPIO31
SPID	35	I/O/T	VDD_SPI	SPID, GPIO32
SPICLK_N	36	I/O/T	VDD_SPI	SPICLK_N_DIFF, GPIO48, SUBSPICLK_N_DIFF
SPICLK_P	37	I/O/T	VDD_SPI	SPICLK_P_DIFF, GPIO47, SUBSPICLK_P_DIFF
GPIO33	38	I/O/T	VDD3P3_CPU / VDD_SPI	SPIIO4, GPIO33, FSPIHD, SUBSPIHD
GPIO34	39	I/O/T	VDD3P3_CPU / VDD_SPI	SPIIO5, GPIO34, FSPICS0, SUBSPICS0
GPIO35	40	I/O/T	VDD3P3_CPU / VDD_SPI	SPIIO6, GPIO35, FSPID, SUBSPID
GPIO36	41	I/O/T	VDD3P3_CPU / VDD_SPI	SPIIO7, GPIO36, FSPICLK, SUBSPICLK
GPIO37	42	I/O/T	VDD3P3_CPU / VDD_SPI	SPIDQS, GPIO37, FSPIQ, SUBSPIQ
GPIO38	43	I/O/T	VDD3P3_CPU	GPIO38, FSPIWP, SUBSPIWP
MTCK	44	I/O/T	VDD3P3_CPU	MTCK, GPIO39, CLK_OUT3, SUBSPICS1
MTDO	45	I/O/T	VDD3P3_CPU	MTDO, GPIO40, CLK_OUT2
VDD3P3_CPU	46	P_D	-	Input power supply for CPU IO
MTDI	47	I/O/T	VDD3P3_CPU	MTDI, GPIO41, CLK_OUT1
MTMS	48	I/O/T	VDD3P3_CPU	MTMS, GPIO42
U0TXD	49	I/O/T	VDD3P3_CPU	U0TXD, GPIO43, CLK_OUT1
U0RXD	50	I/O/T	VDD3P3_CPU	U0RXD, GPIO44, CLK_OUT2
GPIO45	51	I/O/T	VDD3P3_CPU	GPIO45
GPIO46	52	I/O/T	VDD3P3_CPU	GPIO46
XTAL_N	53	-	-	External crystal output

Name	No.	Type	Power Domain	Function
XTAL_P	54	-	-	External crystal input
VDDA	55	P_A	-	Analog power supply
VDDA	56	P_A	-	Analog power supply
GND	57	G	-	Ground

1 P: power pin; PA: analog power pin; PD: digital power pin; I: input; O: output; T: high impedance.
2 Pin functions in bold font are the default pin functions.
3 Power supply for GPIO33, GPIO34, GPIO35, GPIO36 and GPIO37 is configurable to be either VDD3P3_CPU (default) or VDD_SPI.
4 The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to ESP32-S3 Technical Reference Manual.

2.3Pin Name Description
The explanation of each pin name is briefly described below.

Table 3: Pin Name Description

Pin Name	Description
GPIOx	General-purpose input and output (x is GPIO number). GPIO pins can be assigned various functions, including digital and analog functions. For more information on digital functions, please refer to Table 5.
SPIx	SiP flash/PSRAM and external flash/RAM interface (x is CLK, CS0, CS1, D, Q, WP, HD, IO4~7 or DQS).
XTAL_32K_P/N	32 KHz external clock input/output (connecting to ESP32-S3's oscillator). P/N means differential clock positive/negative.
XTAL_P/N	External clock input/output (connecting to ESP32-S3's oscillator). P/N means differential clock positive/negative.
U0RXD/U0TXD	UART0 receive/transmit signals.
MTCK/MTDO/MTDI/MTMS	JTAG interface signals.
LNA_IN	Low-Noise Amplifier (RF LNA) input/output signals.
CHIP_PU	Chip power up pin.
GND	External ground connection.
VDDA	Power supply for analog domain.
VDD3P3_RTC	Power supply for RTC digital domain.
VDD3P3_CPU	Power supply for digital domain.
VDD_SPI	Power supply for SPI IOs.

2.4Function Name Description
The explanation of each function name is briefly described below.

Table 4: Function Name Description

Function Name	Description
RTC_GPIOx	RTC domain GPIO function for low power management.
TOUCHx	Analog function for touch sensing.
ADCx_CHy	Analog to digital conversion channel (x is ADC number, y is channel number).
SUBSPIx	Sub-SPI0/1 bus, differing from SPIx bus (x is CLK, CS0, CS1, D, Q, WP or HD), used for different voltage level of flash and PSRAM
FSPIx	8-line Fast-SPI2 bus function (x is CLK, CS0, CS1, D, Q, WP, HD, IO4~7 or DQS)
SPIx	SPI0/1 bus function (x is CLK, CS0, CS1, D, Q, WP, HD, IO4~7 or DQS)
UxRTS/UxCTS	UARTx hardware flow control signals (x is UART number).
U1RXD/U1TXD	UART1 receive/transmit signals.
CLK_OUTx	Clock output for debug (x is clock number).
USB_D-/USB_D+	USB OTG and USB Serial/JTAG function. USB signal is a differential signal transmitted over a pair of D+ and D- wires.
SPICLK_N/P_DIFF	Serial peripheral interface differential clock negative/positive.

2.5GPIO Functions
ESP32-S3 has 45 GPIO pins (numbering 22-25 is not used) which can be assigned various functions as listed in Table 5. The functions listed here are digital functions (F0-F4). RTC functions and analog functions can be found in Table 2.
Table 5: GPIO Functions

GPIO

Pin Name

Type

At Reset

After Reset

Notes

GPIO0

I/O/T

GPIO0

I/O/T

IE1, WPU1

GPIO1

I/O/T

GPIO1

I/O/T

IE1

GPIO2

I/O/T

GPIO2

I/O/T

IE1

GPIO3

I/O/T

GPIO3

I/O/T

IE1

GPIO4

I/O/T

GPIO4

I/O/T

IE0

GPIO5

I/O/T

GPIO5

I/O/T

IE0

GPIO6

I/O/T

GPIO6

I/O/T

IE0

GPIO7

I/O/T

GPIO7

I/O/T

IE0

GPIO8

I/O/T

GPIO8

I/O/T

SUBSPICS1

O/T

IE0

GPIO9

I/O/T

GPIO9

I/O/T

SUBSPIHD

I1/O/T

FSPIHD

I1/O/T

IE0

IE1

GPIO10

I/O/T

GPIO10

I/O/T

FSPIIO4

I1/O/T

SUBSPICS0

O/T

FSPICS0

I1/O/T

IE0

IE1

GPIO11

I/O/T

GPIO11

I/O/T

FSPIIO5

I1/O/T

SUBSPID

I1/O/T

FSPID

I1/O/T

IE0

IE1

GPIO12

I/O/T

GPIO12

I/O/T

FSPIIO6

I1/O/T

SUBSPICLK

O/T

FSPICLK

I1/O/T

IE0

IE1

GPIO13

I/O/T

GPIO13

I/O/T

FSPIIO7

I1/O/T

SUBSPIQ

I1/O/T

FSPIQ

I1/O/T

IE0

IE1

GPIO14

I/O/T

GPIO14

I/O/T

FSPIDQS

O/T

SUBSPIWP

I1/O/T

FSPIWP

I1/O/T

IE0

IE1

XTAL_32K_P

GPIO15

I/O/T

GPIO15

I/O/T

U0RTS

IE0

XTAL_32K_N

GPIO16

I/O/T

GPIO16

I/O/T

U0CTS

IE0

GPIO17

I/O/T

GPIO17

I/O/T

U1TXD

IE0

IE1

GPIO18

I/O/T

GPIO18

I/O/T

U1RXD

CLK_OUT3

IE0

IE1

GPIO19

I/O/T

GPIO19

I/O/T

U1RTS

CLK_OUT2

IE0

GPIO20

I/O/T

GPIO20

I/O/T

U1CTS

CLK_OUT1

IE0

GPIO21

I/O/T

GPIO21

I/O/T

IE0

SPICS1

O/T

GPIO26

I/O/T

IE1, WPU1

SPIHD

I1/O/T

GPIO27

I/O/T

IE1, WPU1

SPIWP

I1/O/T

GPIO28

I/O/T

IE1, WPU1

SPICS0

O/T

GPIO29

I/O/T

IE1, WPU1

GPIO

Pin Name

Type

At Reset

After Reset

Notes

SPICLK

O/T

GPIO30

I/O/T

IE1, WPU1

SPIQ

I1/O/T

GPIO31

I/O/T

IE1, WPU1

SPID

I1/O/T

GPIO32

I/O/T

IE1, WPU1

GPIO33

I/O/T

GPIO33

I/O/T

FSPIHD

I1/O/T

SUBSPIHD

I1/O/T

SPIIO4

I1/O/T

IE0

IE1

GPIO34

I/O/T

GPIO34

I/O/T

FSPICS0

I1/O/T

SUBSPICS0

O/T

SPIIO5

I1/O/T

IE0

IE1

GPIO35

I/O/T

GPIO35

I/O/T

FSPID

I1/O/T

SUBSPID

I1/O/T

SPIIO6

I1/O/T

IE0

IE1

GPIO36

I/O/T

GPIO36

I/O/T

FSPICLK

I1/O/T

SUBSPICLK

O/T

SPIIO7

I1/O/T

IE0

IE1

GPIO37

I/O/T

GPIO37

I/O/T

FSPIQ

I1/O/T

SUBSPIQ

I1/O/T

SPIDQS

I0/O/T

IE0

IE1

GPIO38

I/O/T

GPIO38

I/O/T

FSPIWP

I1/O/T

SUBSPIWP

I1/O/T

IE0

IE1

MTCK

GPIO39

I/O/T

CLK_OUT3

SUBSPICS1

O/T

IE0

IE1, or
IE1&WPU1

MTDO

O/T

GPIO40

I/O/T

CLK_OUT2

IE0

IE1

MTDI

GPIO41

I/O/T

CLK_OUT1

IE0

IE1

MTMS

GPIO42

I/O/T

IE0

IE1

U0TXD

GPIO43

I/O/T

CLK_OUT1

IE1, WPU1

U0RXD

GPIO44

I/O/T

CLK_OUT2

IE1, WPU1

GPIO45

I/O/T

GPIO45

I/O/T

IE1, WPD1

GPIO46

I/O/T

GPIO46

I/O/T

IE1, WPD1

SPICLK_P

SPICLK_P_DIFF

O/T

GPIO47

I/O/T

SUBSPI-
CLK_P_DIFF

O/T

IE1

SPICLK_N

SPICLK_N_DIFF

O/T

GPIO48

I/O/T

SUBSPI-
CLK_N_DIFF

O/T

IE1

Please refer to the next page for more information on GPIO functions.

Type
Each digital function (Fn, n=0~4) is associated with a "Type". The description of "Type" is as follows:
•O: Output only.
•O/T: The signal can be output or high-impedance.
•I/O/T: The signal can be input, output, and high-impedance.
•I1: Input only. If the pin is assigned a function other than Fn, the input signal of Fn is always "1".
•I1/O/T: The signal can be input, output, and high-impedance. If Fn is not selected, the input signal of Fn is always "1".
•I0/O/T: The signal can be input, output, and high-impedance. If Fn is not selected, the input signal of Fn is always "0".
At Reset/After Reset
The default configuration of each pin at reset and after reset:
•IE0 - input disabled
•IE1 - input enabled
•IE1, WPD1 - input enabled, internal weak pull-down resistor enabled
•IE1, WPU1 - input enabled, internal weak pull-up resistor enabled
•IE1, or IE1&WPU1 - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is 1, the MTCK pin floats after chip reset (IE1)
0, the MTCK pin connects to internal weak pull-up resistor after chip reset (IE1&WPU1)
Notes
•R - These pins have RTC or analog functions.
Drive Strength
•The default drive strength of GPIO27~32 is 2'd3 (~40 mA).
•The default drive strength of other pins is 2'd2 (~20 mA).

2.6PintoPin Mapping Between Chip and SiP Flash/PSRAM
Table 6 lists the pin-to-pin mapping between the chip and the SiP flash/PSRAM. The chip pins listed here are not recommended for other usage. For the data port connection between ESP32-S3 and external flash please refer to Section 3.4.2.
Table 6: PintoPin Mapping Between Chip and SiP Flash/PSRAM

ESP32S3FN8	SiP flash (8 MB, Quad SPI)
SPICLK	CLK
SPICS0	CS#
SPID	DI
SPIQ	DO
SPIWP	WP#
SPIHD	HOLD#
ESP32S3R2	SiP PSRAM (2 MB, Quad SPI)

SPICLK	CLK
SPICS1	CE#
SPID	SI/SIO0
SPIQ	SO/SIO1
SPIWP	SIO2
SPIHD	SIO3
ESP32S3R8 / ESP32S3R8V	SiP PSRAM (8 MB, Octal SPI)
SPICLK	CLK
SPICS1	CE#
SPID	DQ0
SPIQ	DQ1
SPIWP	DQ2
SPIHD	DQ3
GPIO33	DQ4
GPIO34	DQ5
GPIO35	DQ6
GPIO36	DQ7
GPIO37	DQS/DM

2.7Power Scheme
ESP32-S3 has four input power pins:
•VDDA1
•VDDA2
•VDD3P3_RTC
•VDD3P3_CPU
And one input/output power pin:
•VDD_SPI
VDDA1 and VDDA2 are the input power supply for the analog domain.
VDD_SPI can be an input power supply or output power supply. It can be powered by Flash Voltage Regulator (nominal 1.8 V) or by VDD3P3_RTC via RSP I (nominal 3.3 V). As the SiP flash/PSRAM in ESP32-S3FN8, ESP32-S3R2, and ESP32-S3R8 operates at 3.3 V, VDD_SPI must be powered by VDD3P3_RTC via RSP I . Software can power off VDD_SPI to minimize current leakage of flash in Deep-sleep mode.
VDD3P3_RTC is the input power supply for Low Power Voltage Regulator that powers the RTC domain.
VDD3P3_CPU and VDD3P3_RTC power Digital System Voltage Regulator at the same time that further powers the Digital System domain.
VDD3P3_RTC is the input power supply for RTC IO. VDD3P3_CPU is the input power supply for Digital IO. VDD_SPI is the input power supply for SPI IO.
Either VDD_SPI or VDD3P3_CPU can be selected as the input power supply for SPI/Digital IO.

Software can read the values of corresponding bits from register "GPIO_STRAPPING".
During the chip's system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as strapping bits of "0" or "1", and hold these bits until the chip is powered down or shut down.
GPIO0, GPIO45 and GPIO46 are connected to the chip's internal weak pull-up/pull-down during the chip reset. Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak pull-up/pull-down will determine the default input level of these strapping pins.
GPIO3 is floating by default. Its strapping value can be configured to determine the source of the JTAG signal inside the CPU, as shown in Table 9. In this case, the strapping value is controlled by the external circuit that cannot be in a high impedance state. Table 8 shows more configuration combinations of EFUSE_DIS_USB_JTAG, EFUSE_DIS_PAD_JTAG, and EFUSE_STRAP_JTAG_SEL that determine the JTAG signal source.
Table 8: JTAG Signal Source Selection

EFUSE_STRAP_JTAG_SEL	EFUSE_DIS_USB_JTAG	EFUSE_DIS_PAD_JTAG	JTAG Signal Source
1	0	0	Refer to Table 9
0	0	0	USB Serial/JTAG controller
don't care	0	1	USB Serial/JTAG controller
don't care	1	0	On-chip JTAG pins
don't care	1	1	N/A

To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host MCU's GPIOs to control the voltage level of these pins when powering on ESP32-S3.
After reset, the strapping pins work as normal-function pins. Refer to Table 9 for a detailed configuration of the strapping pins.
Table 9: Strapping Pins

VDD_SPI Voltage ¹
Pin	Default	3.3 V	1.8 V
GPIO45	Pull-down	0	1
Booting Mode ²
Pin	Default	SPI Boot	Download Boot
GPIO0	Pull-up	1	0
GPIO46	Pull-down	Don't care	0
Enabling/Disabling ROM Messages Print During Booting ³ ⁴
Pin	Default	Enabled	Disabled
GPIO46	Pull-down	See the fourth note	See the fourth note
JTAG Signal Selection

Pin	Default	EFUSE_DIS_USB_JTAG = 0, EFUSE_DIS_PAD_JTAG = 0, EFUSE_STRAP_JTAG_SEL=1
GPIO3	N/A	0: JTAG signal from on-chip JTAG pins 1: JTAG signal from USB Serial/JTAG controller

Note:
1.VDD_SPI voltage is determined either by the strapping value of GPIO45 or by VDD_SPI_TIEH. When EFUSE_VDD_SPI_FORCE is 0, VDD_SPI voltage is determined by the strapping value of GPIO45; when EFUSE_VDD_SPI_FORCE is 1, VDD_SPI voltage is determined by VDD_SPI_TIEH.
2.The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior.
3.ROM boot messages can be printed over U0TXD (by default) or GPIO17 (U1TXD), depending on the eFuse bit EFUSE_UART_PRINT_CHANNEL.
4.When both EFUSE_DIS_USB_SERIAL_JTAG and EFUSE_DIS_USB_OTG are 0, ROM boot messages will be printed to the USB Serial/JTAG controller. Otherwise, the messages will be printed to UART, controlled by GPIO46 and EFUSE_UART_PRINT_CONTROL. Specifically, when EFUSE_UART_PRINT_CONTROL value is:
0, print is normal during boot and not controlled by GPIO46.
1 and GPIO46 is 0, print is normal during boot; but if GPIO46 is 1, print is disabled. 2 and GPIO46 is 0, print is disabled; but if GPIO46 is 1, print is normal.
3, print is disabled and not controlled by GPIO46.

3.Functional Description
3.1CPU and Memory
3.1.1CPU
ESP32-S3 has a low-power Xtensa® dual-core 32-bit LX7 microprocessor with the following features:
•Five-stage pipeline that supports the clock frequency of up to 240 MHz
•16-bit/24-bit instruction set providing high code density
•32-bit customized instruction set and 128-bit data bus that provide high computing performance
•Support for single-precision floating-point unit (FPU)
•32-bit multiplier and 32-bit divider
•Unbuffered GPIO instructions
•32 interrupts at six levels
•Windowed ABI with 64 physical general registers
•Trace function with TRAX compressor, up to 16 KB trace memory
•JTAG for debugging

3.1.2Internal Memory
ESP32-S3's internal memory includes:
•384 KB ROM: for booting and core functions
•512 KB onchip SRAM: for data and instructions, running at a configurable frequency of up to 240 MHz
•RTC FAST memory: 8 KB SRAM that supports read/write/instruction fetch by the main CPU (LX7 dual-core processor). It can retain data in Deep-sleep mode.
•RTC SLOW Memory: 8 KB SRAM that supports read/write/instruction fetch by the main CPU (LX7 dual-core processor) or coprocessors. It can retain data in Deep-sleep mode.
•4 kbit eFuse: 1652 bits are reserved for user data, such as encryption key and device ID.
•SiP flash and PSRAM: See details in Table 1 Comparison.

3.1.3External Flash and RAM
ESP32-S3 supports SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to multiple external flash and RAM.
The external flash and RAM can be mapped into the CPU instruction memory space and read-only data memory space. The external RAM can also be mapped into the CPU data memory space. ESP32-S3 supports up to 1 GB of external flash and RAM, and hardware encryption/decryption based on XTS-AES to protect users' programs and data in flash and external RAM.
Through high-speed caches, ESP32-S3 can support at a time up to:
•External flash or RAM mapped into 32 MB instruction space as individual blocks of 64 KB
•External RAM mapped into 32 MB data space as individual blocks of 64 KB. 8-bit, 16-bit, 32-bit, and 128-bit reads and writes are supported. External flash can also be mapped into 32 MB data space as individual blocks of 64 KB, but only supporting 8-bit, 16-bit, 32-bit and 128-bit reads.

3.1.5Cache
ESP32-S3 has an instruction cache and a data cache shared by the two CPU cores. Each cache can be partitioned into multiple banks and has the following features:
•Instruction cache: 16 KB (one bank) or 32 KB (two banks) Data cache: 32 KB (one bank) or 64 KB (two banks)
•Instruction cache: four-way or eight-way set associative

Data cache: four-way set associative
•Block size of 16 bytes or 32 bytes for both instruction cache and data cache
•Pre-load function
•Lock function
•Critical word first and early restart

3.2System Clocks
3.2.1CPU Clock
The CPU clock has three possible sources:
•External main crystal clock
•Internal fast RC oscillator (typically about 17.5 MHz, and adjustable)
•PLL clock
The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2.

3.2.2RTC Clock
The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible sources:
•External low-speed (32 kHz) crystal clock
•Internal slow RC oscillator (typically about 136 kHz, and adjustable)
•Internal fast RC oscillator divided clock (derived from the internal fast RC oscillator divided by 256) The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:
•External main crystal clock divided by 2
•Internal fast RC oscillator (typically about 17.5 MHz, and adjustable)

3.3Analog Peripherals
3.3.1AnalogtoDigital Converter (ADC)
ESP32-S3 integrates two 12-bit SAR ADCs and supports measurements on 20 channels (analog-enabled pins). For power-saving purpose, the ULP coprocessors in ESP32-S3 can also be used to measure voltage in sleep modes. By using threshold settings or other methods, we can awaken the CPU from sleep modes.

3.3.2Temperature Sensor
The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value.
The temperature sensor has a range of -20 °C to 110 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors such as microcontroller clock frequency or I/O load. Generally, the chip's internal temperature is higher than the ambient temperature.

3.3.3Touch Sensor
ESP32-S3 has 14 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points can be detected. The touch sensing performance can be further enhanced by the waterproof design and digital filtering feature.

3.4Digital Peripherals
3.4.1General Purpose Input / Output Interface (GPIO)
ESP32-S3 has 45 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC, touch sensing,
etc.
All GPIOs have selectable internal weak pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register. Input GPIOs can also be set to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional,
non-inverting, and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as UART, SPI, etc. For low-power operations, the GPIOs can be set to holding
state.
The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pads. Together they provide highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pads while peripheral output signals can be configured to any IO pad. For more information about IO MUX and GPIO matrix, please refer to ESP32-S3 Technical Reference Manual.

3.4.2Serial Peripheral Interface (SPI)
ESP32-S3 features four SPI interfaces (SPI0, SPI1, SPI2 and SPI3). SPI0 and SPI1 can be configured to operate in SPI memory mode; SPI2 and SPI3 can be configured to operate in general-purpose SPI mode.
•SPI Memory mode
In SPI memory mode, SPI0 and SPI1 interface with external SPI memory. Data transmission is in multiples of bytes. Up to 8-line SDR/DDR (Single Data Rate/Double Data Rate) reads and writes are supported. The clock frequency is configurable to a maximum of 120 MHz for OPI SDR/DDR mode.
•SPI2 Generalpurpose SPI (GPSPI) mode
SPI2 can operate in master and slave modes. The master mode supports two-line full-duplex communication and single-/two-/four-/eight-line half-duplex communication. The slave mode supports two-line full-duplex communication and single-/two-/four-line half-duplex communication. The host's clock frequency is configurable. Data transmission is in multiples of bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface supports DMA.
-In two-line full-duplex communication mode, the host's clock frequency is configurable to 80 MHz at most, and the slave's clock frequency to 60 MHz at most. Four modes of SPI transfer format are supported. Only SDR reads and writes are supported.
-In single-/two-/four-/eight-line half-duplex communication mode, the host's clock frequency is configurable to 80 MHz at most for SDR reads/writes and 40 MHz for DDR reads/writes. Four modes of SPI transfer format are supported.

-In single-/two-/four-line half-duplex communication mode, the slave's clock frequency is configurable to 60 MHz at most. Only SDR reads and writes are supported. Four modes of SPI transfer format are supported.
•SPI3 Generalpurpose SPI (GPSPI) mode
SPI3 can operate in master and slave modes, in two-line full-duplex and single-line, two-line and four-line half-duplex communication modes. Only SDR reads and writes are supported. The host's clock frequency is configurable. Data transmission is in multiples of bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI3 interface supports DMA.
-In two-line full-duplex communication mode, the host's clock frequency is configurable to a maximum of 80 MHz, and the slave's clock frequency to a maximum of 60 MHz. Four modes of SPI transfer format are supported.
-In single-line, two-line and four-line half-duplex communication mode, the host's clock frequency is configurable to a maximum of 80 MHz, and the slave's clock frequency to 60 MHz at most. Four modes of SPI transfer format are supported.

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Company Introduction: Shenzhen Ferry Technology Co., Ltd. Has been focusing on the optimization and construction of wireless communication transmission mechanism and wireless audio and video transmission solution level to provide WiFi module company, unremitting in-depth development of WiFi wireless transmission, radar induction and other low-power IOT scene microwave radar manufacturers, We are committed to bringing rich and diverse data and information into every person, home, and organization in an easily accessible way, building a smart world that connects everything: Connecting everywhere and connecting our lives to each other; Let wireless transmission without boundaries, so that intelligence at your fingertips.

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